As the design rule for DRAM capacitors has been scaled down to below submicron dimensions, many efforts have been made to reduce electrical short circuiting (shorting) of lower electrodes and to more effectively arrange lower electrodes within an area on a semiconductor substrate. An electrical short of a lower electrode of a capacitor may occur when photolithography and etch processes of a semiconductor fabrication process are pushed to the limits of allowable process margins. Further, an electrical short of a lower electrode may occur because surface areas of the lower electrodes may be maintained the same size in order to maintain the capacitance of capacitors, even as the design rule is decreased. To do so, there has been proposed a method of placing conductive layer patterns below respective lower electrodes, in order to use upper spaces on a semiconductor substrate more effectively. The conductive layer patterns may be covered with the same interlayer insulating layer as the lower electrodes. Further, the conductive layer patterns may allow the lower electrodes to be electrically connected to the semiconductor substrate.
However, while providing conductive layer patterns on the semiconductor substrate may reduce the occurrence of electrical shorts of the lower electrodes, such a DRAM device may not have good electrical characteristics due to the conductive layer patterns. This is because electrical shorts of the conductive layer patterns may occur when a scaled-down design rule is used. An electrical short of the conductive layer patterns may deteriorate the electrical characteristics of a DRAM capacitor.
A method of forming a capacitor is disclosed in U.S. Pat. No. 6,294,426 entitled “Method Of Fabricating A Capacitor Under Bit Line Structure With Increased Capacitance Without Increasing The Aspect Ratio For A Dry Etched Bit Line Contact Hole” to Kuo-Chi Tu, et. al.
According to Kuo-Chi Tu, et. al, the method includes sequentially forming transfer gate transistors, capacitor structures and a bit line structure on a semiconductor substrate. Conductive plugs are formed between the bit line structure and the semiconductor substrate and between the capacitor structures and the semiconductor substrate respectively. At this time, the conductive plugs disposed between the capacitor structures and the semiconductor substrate have heights lower than those of the conductive plugs between the bit line structure and the semiconductor substrate. The method provides a way of increasing the capacitance of a capacitor by increasing the areas of lower electrodes, using the height difference of the conductive plugs.
However, the method described by Kuo-Chi Tu et al. may have a limited ability to increase the capacitance of a capacitor in semiconductor fabrication processes having a submicron design rule. This is because the lower electrodes are related to the height of the bit line structure in a CUB (capacitor under a bit line) structure. Further, since the bit line structure exists between the lower electrodes, there may be a very small allowance margin in the semiconductor fabrication processes to prevent electrical shorts of the lower electrodes.